Security Auditable System-on-a-Chip for mass volume - Team Build

Libre-SOC are the independent development group at the core of the technology RED Semiconductor will be bringing to market. We are moving forward rapidly with our first test chip going into FAB in a weeks’ time (9th June) and we are close to running a basic Linux implementation on an FPGA.

Our plan is to develop a security auditable System-on-a-Chip for mass volume applications in power-efficient hybrid 3D GPU and VPU workloads, as well as accelerated cryptographic, embedded network and communication applications.

We now need to accelerate our efforts and are looking to increase the size of the team. Currently we are funded by grants against delivered objectives and we have funded capacity for specific tasks in hand.

We are going to be using this project activity to assess members of the future engineering team for RED Semiconductor.

Our design methodology is unconventional, however is easily understood if you have a reasonable level of expertise in electronic engineering or software and are willing to learn.

That said there are some areas where certain levels of expertise will have an easier time. these are:

* Verilog, VHDL, FPGA or gate-level electronics experience

* Assembler (of any kind), c, or c++

* Working with Libre / Open Projects

* Engineering background and training

* Self-taught ("auto-didact")

* python 3

* yosys and other VLSI synthesis tools

If you are interested in participating, please contact Luke Leighton at lkcl@libre-soc.org, and join the public mailing list at http://lists.libre-soc.org/mailman/listinfo/libre-soc-dev.